The present invention relates to a method and device for controlling memory access, and more particularly to a device for controlling memory access for use in a Universal Serial Bus (USB) system.
As is known, the USB is an industry standard cable bus which functions to support data exchange between a host computer (e.g., PC) and various peripheral devices. The USB interface to the host computer is referred to as the host controller.
FIG. 1 illustrates a typical prior art system for transferring data between a host PC and a peripheral device utilizing a USB. As shown, the system comprises a host PC 2, which is coupled to the USB core 10 (i.e., the host controller) via a standard USB bus interface 4. The USB core 10 is also coupled to a memory control unit (MCU) 20 via bus interface 6. As illustrated, the bus interface 6 comprises IRQ request line 21, read/write request line 22, an address bus 23 and a data bus 24. It is noted that typically, the USB core 10 and the MCU 20 are contained in the peripheral device coupled to the host PC 2.
The USB core 10 comprises serial interface engine (SIE) 11, a general function interface (GFI) 12, which is coupled to the SIE 11, and a first-in, first-out memory (FIFO) 13, which is coupled to both the SIE 11 and the GFI 12. The memory controller, hereafter referred to as the MCU 20, comprises a microprocessor unit (MPU) 21, a direct memory access unit (DMA) 22, and a memory unit 25. As shown, the IRQ request line 21, the r/w request line 22, the address bus 23 and the data bus 24 are all coupled between the GFI 12 and the MPU 21. In addition, r/w request line 22, the address bus 23 and the data bus 24 are also coupled to the memory unit 25. Finally, the DMA unit 22 is coupled to both the address bus 23 and the MPU 21.
In operation, the USB core 10 functions in-part to control the transfer of data between the host PC 2 and the MCU 20. Specifically, data transferred from the host PC 2 to the USB core 10 is received by the SIE 11 and stored in the FIFO memory 13. Once the data is received and placed in the FIFO memory 13, the SIE 11 generates a control signal which is coupled to the GFI 12 via control line 17 and which instructs the GFI 12 to generate an IRQ request signal. The IRQ request signal is transferred to the MPU 21 of the MCU 20. The IRQ request functions to inform the MCU 20 that data to be transferred to the MCU 20 is in the FIFO memory 13.
Upon receipt of the IRQ request signal, the MCU 20 releases the address bus 23 and the data bus 24 to the DMA unit 22. The DMA unit 22 then functions to transfer the data from the FIFO memory 13 to memory unit 25 via data bus 24. Upon completion of the transfer of data to the memory unit 25, the DMA unit 22 informs the MPU 21 that data transfer is complete, and then the MPU 21 reads the data stored in the memory unit 25, and performs the command(s)/instruction(s) contained in the data.
Upon completion of performing the command, the MPU 21 writes the results associated with the given command back to the memory unit 25. Once the data is stored in memory unit 25, the MPU 21 informs the USB core 10 that it is ready to transfer data back to thehost PC 2 by forwarding a signal to the GFI 12 via the R/W request line 22. The MPU 21 also releases the address bus 23 and the data bus 24 to the DMA unit 22, so that the DMA unit can effect transfer to the data stored in memory unit 25 to the FIFO memory 13 via the GFI 12. Upon receipt of a signal from the GFI 12 indicating that data transfer is complete, the SIE 11 transfers data to the host PC 2.
FIG. 2 illustrates the sequence of the data transfer process described above regarding the transfer of data from the USB core 10 to the MCU 20, and vica versa. In the first step, data is transferred from the host PC 2 to the SIE 11, and the SIE 11 stores the data in the FIFO memory 13. Next, in step (*1), upon receipt of the IRQ signal generated by the GFI 12, the MPU 21 releases the address bus 23 and the data bus 24, thereby making the DMA unit 22 active. Next, in steps (*2, *3), both the DMA unit 22 and the memory unit 25 are active, as the DMA unit 22 functions to transfer data contained in the FIFO memory 13 and store the data in the memory unit 25. Next, in step (*4), the MPU 21 reads the data from the memory unit 25 and performs the command set forth in the data. Next, in steps (*5, *6), the MPU 21 writes the data that will be transferred to the host PC 2 into the memory unit 25. Next, in step (*7), the MPU 21 once again releases the address bus 23 and the data bus 24 so as to make the DMA unit 22 active. Then, in steps (*8, *9), the DMA unit 22 functions to transfer the data in the memory unit 25 to the FIFO memory 13. It is noted that the MPU 21 generates a signal which is coupled to the GFI 12 indicating that data is ready to be sent to the USB core 10. Finally, in step (*10), the data stored in the FIFO memory 13 is transferred to the host PC 2 by the SIE 11.
Notwithstanding the ability of the USB core 10 and the MCU 20 to transfer data to and from the host PC 2, the foregoing prior art design suffers from the following problems. Most significantly, as explained above, the MCU 21 utilizes a DMA unit 22 to effect transfer of data to and from the USB core 10. As such, because the MPU 21, the DMA unit 22 and the memory unit 25 all utilize the same bus structure, during data transfer the MPU 21 must release the buses to the DMA unit 22. As a result, during the data transfer period, the MPU 21 is effectively prevented from performing any functions. Thus, the overall operational efficiency of the system is degraded. In addition, as the DMS unit 22 is utilized in all data transfers, the time required to complete such transfers is undesirable increased.
Furthermore, as memory unit 23 and FIFO memory 13 represent predefined memory components having a fixed size, it is always necessary to allocate a fixed amount of memory for both the FIFO memory 13 and a memory unit 23, which is sufficient to handling the data transfer loads anticipated in a given application. Such an implementation can disadvantageously result in the under utilization of the available memory.
Accordingly, there is exists a need for a device capable of effecting the transfer of data between a host PC and memory, which allows for a decrease in the time required to complete the data transfer and which allows a microprocessor unit contained in the device to perform tasks during the memory transfer process. In addition, there is also a need for a device for controlling memory access which minimizes the memory requirements of the system utilizing a USB interface.
In an effort to solve the aforementioned needs, it is an object of the present invention to provide a device for controlling memory access capable of effecting the transfer of data between a host PC and memory, which allows for a decrease in the time required to complete the data transfer and which allows a microprocessor unit contained in the device to perform tasks during the memory transfer process. It is also an object of the present invention to minimize the memory requirements of the system utilizing an USB interface.
In accordance with a first exemplary embodiment, the present invention relates to a device for controlling memory access which includes an interface unit for receiving data from an external source, and a memory control unit coupled to the interface unit. The memory control unit includes a microprocessor unit, a main memory unit and a shared memory unit. The microprocessor unit is capable of storing and retrieving data from the main memory unit. Both the microprocessor unit and the interface unit are capable of storing and retrieving data from the shared memory unit. The device further includes a first bus for coupling the interface unit to the microprocessor; a second bus for coupling the interface unit to the shared memory unit; and bus arbitration logic coupled to both the first bus and the second bus. The bus arbitration logic is operative for allowing the microprocessor to access the main memory unit of the memory control during the time period the interface unit is storing data in, or retrieving data from, the shared memory unit.
The present invention also relates to a method of controlling data transfer between an interface unit and a memory controller. The method comprises the steps of inputting external data to be transferred to the memory control unit into the interface unit; transferring the external data input into the interface unit directly into a shared memory unit, which forms part of the memory controller; generating a first control signal after the external data has been stored in the shared memory unit by the interface unit, where the control signal is operative for controlling bus arbitration logic functioning to allow a microprocessor unit forming part of the memory controller to access the shared memory unit; processing the data stored in the shared memory unit and storing any resultant data in the shared memory unit, generating a second control signal after the resultant data has been stored in the shared memory unit by the microprocessor, where the second control signal is operative for controlling the bus arbitration logic so as to prevent the microprocessor unit from accessing the shared memory unit; and retrieving the resultant data stored in the shared memory unit, where the resultant data is retrieved directly by the interface unit.
As described in further detail below, the present invention provides significant advantages over the prior art. Most importantly, as the design of the present invention eliminates the requirement of the DMA unit and allows the USP core to directly store data into the shared memory contained in the MCU, the present invention significantly reduces the time required to transfer data between the USB core and the MCU. In fact, it is estimated that the present invention reduces the transfer time by xc2xd in comparison to the device illustrated in FIG. 1.
In addition, as the present design eliminates the need for the DMA unit contained in the MCU and the FIFO memory in the USB core, the design of the present invention represents a cost savings in comparison with prior art designs.
Another advantage associated with the present invention is that it provides the programmer extreme flexibility with regard to amount of the memory to allocate to the shared memory. More specifically, the programmer may readily vary the size of the shared memory in accordance with the given application to be executed. Moreover, any memory space not allocated to the shared memory can be allocated to the main memory unit of the MPU.
Yet another advantage is that even though the shared memory is typically accessible by the USB core, the design of the present invention allows the MPU to access memory and execute commands simultaneously with the storage of data in the shared memory by the USB core. Accordingly, in contrast to the device illustrated in FIG. 1, the present design functions to increase the overall operational speed of the device.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.